OV Camera

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Type Mega pixels
OV7670 30 MP
OV7725 30 MP
OV2640 200 MP

Features

OV7725

  • Up to 60fps on VGA mode
  • Can be through the SCCB interface, in fact, is similar to the I2C interface, the white balance, gama, color correction, exposure control, color control.
  • sclk and sdat need 4.7K pull-up

FIFO

Basic Principle

OV7670 FIFO camera, image sensor and image buffer pieces AL422B combine to solve the problem of low-end microcontroller image acquisition speed bottleneck. Basic principle:
FIFO to MCU.jpg
User according to the figure above simply the fifo read data timing control pin, data can be read directly by the MCU IO port data into memory or sent to the screen memory display can be operated by low-speed MCU control, and simple processing of the data, such as black and white identification.
The OV7670 with FIFO module, image acquisition and control with buffer storage space a module is able to slow the MCU. This module adds a FIFO (first-in, first-out) memory chips, the same 30w-pixel CMOS image photosensitive chip, 3.6mm focal length of the lens and the lens mount, onboard various power CMOS chip (power requirements are detailed in chip data file), the board at the same time leads to the control pins and data pins, easy to operate and use.
As control sensor pin defined as follows:

Sequence

Using the FIFO as data buffering, data acquisition is greatly simple, users only need to be concerned about is how to read, do not need to worry about how specific data is collected, it can be reduced or even do not care about the CMOS control and timing relationships,image acquisition.
Control sequence is as follows:

Pin Definition

Without FIFO

Basic Pins Description Extra Pins Description note
3V3 supply voltage
GND ground
SIO_C SCCB interface control clock some of the low-level microcontroller needs pull-up control, and the I2C interface similar
SIO_D SCCB interface serial data input (output) same above
VSYNC frame synchronizing signal output signal
HREF line synchronizing signal output signal
PCLK pixel clock output signal
D0-D7 data port output signal
RESTE reset port normal use pulled
PWDN power selection mode normal use pull down
STROBE photographing flash control normal use may not be required
FIFO_RCK FIFO memory read-clock control
FIFO_WR_CTR write control 1 allows the CMOS is written to the FIFO, to prohibit 0
FIFO_OE FIFO off control
FIFO_WRST-FIFO write pointer service end
FIFO_RRST-FIFO read pointer reset end

Schematic, Dimension

Reference

OV7670 - source

OV7670 - Datasheet

OV7670 Demo Code

OV7725 - Datasheet

OV7725 Demo code