CC2500B – 2.4G-Wireless Module

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Contents

Demo

More Power expecification can refer to Data CC2500 documents

INT8U PaTabel[8] = {0xC0 ,0xC0 ,0xC0 ,0xC0 ,0xC0 ,0xC0 ,0xC0 ,0xC0};

SPI RW operation

INT8U SpiTxRxByte(INT8U dat)
{
   INT8U i,temp;
   temp = 0;
   SCK = 0;
   for(i=0; i<8; i++)
   {
      if(dat & 0x80)
      {
          MOSI = 1;
      }
      else MOSI = 0;
      dat <<= 1;
      SCK = 1;
      _nop_();
      _nop_();
      temp <<= 1;
      if(MISO)temp++;
      SCK = 0;
      _nop_();
      _nop_();  
   }
   return temp;
}

SPI Write Register

void halSpiWriteReg(INT8U addr, INT8U value)
{
   CSN = 0;
   while (MISO);
   SpiTxRxByte(addr);     // Write address
   SpiTxRxByte(value);    // write data
   CSN = 1;
}

SPI Read register operation

INT8U halSpiReadReg(INT8U addr)
{
   INT8U temp, value;
   temp = addr|READ_SINGLE;//read register command
   CSN = 0;
   while (MISO);
   SpiTxRxByte(temp);
   value = SpiTxRxByte(0);
   CSN = 1;
   return value;
}

CC2500 software reset

void RESET_CC2500(void)
{
   CSN = 0;
   while (MISO);
   SpiTxRxByte(CCxxx0_SRES);    //write register command
   while (MISO);
   CSN = 1;
}

CC2500 Initialization

const RF_SETTINGS rfSettings =
{
   0x00,
   0x07,  // FSCTRL1  Frequency synthesizer control.
   0x00,  // FSCTRL0  Frequency synthesizer control.
   0x5C,  // FREQ2    Frequency control word, high byte.
   0x58,  // FREQ1    Frequency control word, middle byte.
   0x9D,  // FREQ0    Frequency control word, low byte.
   0x0E,  // MDMCFG4  Modem configuration.
   0x3B,  // MDMCFG3  Modem configuration.
   0x73,  // MDMCFG2  Modem configuration.
   0x42,  // MDMCFG1  Modem configuration.
   0xF8,  // MDMCFG0  Modem configuration.
 
   0x00,  // CHANNR   Channel number.
0x00, 
 // DEVIATN  Modem deviation setting (when FSK modulation is enabled).
   0xB6,  // FREND1   Front end RX configuration.
   0x10,  // FREND0   Front end RX configuration.
   0x18,  // MCSM0    Main Radio Control State Machine configuration.
   0x1D,  // FOCCFG   Frequency Offset Compensation Configuration.
   0x1C,  // BSCFG    Bit synchronization Configuration.
   0xC7,  // AGCCTRL2 AGC control.
   0x00,  // AGCCTRL1 AGC control.
   0xB2,  // AGCCTRL0 AGC control.
   0xCA,  // FSCAL3   Frequency synthesizer calibration.
   0x0A,  // FSCAL2   Frequency synthesizer calibration.
   0x00,  // FSCAL1   Frequency synthesizer calibration.
   0x11,  // FSCAL0   Frequency synthesizer calibration.
   0x59,  // FSTEST   Frequency synthesizer calibration.
   0x88,  // TEST2    Various test settings.
   0x31,  // TEST1    Various test settings.
   0x0B,  // TEST0    Various test settings.
   0x0B,  // IOCFG2   GDO2 output pin configuration.
0x06,  // IOCFG0D  GDO0 output pin configuration.
   0x05,  // PKTCTRL1 Packet automation control. //address detection 
0x45,  // PKTCTRL0 Packet automation control. 
//The variable length data packets through the first position after the sync word length of the configuration packet
   0x0A,    //the address used for filtering
   0xFF   // PKTLEN   Packet length.   Max
};

Data receive process

INT8U halRfReceivePacket(INT8U *rxBuffer, INT8U *length)
{
   INT8U status[2];
   INT8U packetLength;
   INT8U i=(*length)*4; //depends on datarate and length
   halSpiStrobe(CCxxx0_SRX);     // enter into receive mode
   delay(2);
   while (GDO0)
   {
      delay(2);
      --i;
      if(i<1)
        return 0;    
   }  
if ((halSpiReadStatus(CCxxx0_RXBYTES) & BYTES_IN_RXFIFO))
 //if the received data is not 0
   {
       packetLength = halSpiReadReg(CCxxx0_RXFIFO);
//read first byte, this byte is the length of this data frame
       if (packetLength <= *length)    
//if the lengths of available data needed is less or equal to the received data packet length
      {
halSpiReadBurstReg(CCxxx0_RXFIFO, rxBuffer, packetLength); //read all received data
           *length = packetLength;             
//set the received data length to current data length
// Read the 2 appended status bytes (status[0] = RSSI, status[1] = LQI)
           halSpiReadBurstReg(CCxxx0_RXFIFO, status, 2); 
//read CRC check bit
          halSpiStrobe(CCxxx0_SFRX);     //clear buffer
           return (status[1] & CRC_OK); //if check succeed return success
       }
       else
      {
           *length = packetLength;
           halSpiStrobe(CCxxx0_SFRX);   //clear buffer
           return 0;
       }
   }
   else
   return 0;
}

Data send process

void halRfSendPacket(INT8U *txBuffer, INT8U size)
{
   halSpiWriteReg(CCxxx0_TXFIFO, size);
   halSpiWriteBurstReg(CCxxx0_TXFIFO, txBuffer, size);// write the data which needed to be sent
   halSpiStrobe(CCxxx0_STX);     //enter into send mode to send data
   // Wait for GDO0 to be set -> sync transmitted
   while (!GDO0);
   // Wait for GDO0 to be cleared -> end of packet
   while (GDO0);
      halSpiStrobe(CCxxx0_SFTX);
}