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Revision as of 06:05, 6 September 2019 by Chao (talk | contribs)
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Chip appearance: QFN32 package, 5mm x 5mm

Chip integration

  • integrated 32-bit embedded Cortex-M3 processor, operating frequency 80MHz;
  • Integrated 288KB data storage;
  • Integrated 1MB FLASH;
  • Integrated 8-channel DMA controller, support any channel allocated for hardware use or software use, support 16 hardware applications, support software linked list management;
  • Integrated 2.4G RF transceiver to meet the IEEE802.11 specification;
  • Integrated PA / LNA / TR-Switch;
  • Integrated 32.768KHz clock oscillator;
  • Integrated voltage detection circuit;
  • Integrated LDO;
  • Integrated power control circuit;
  • Integrated power-on reset circuit;
  • Integrated universal encryption hardware accelerator, support for multiple encryption and decryption protocols such as PRNG (Pseudo Random Number Generator) / SHA1 / MD5 / RC4 / DES / 3DES / AES / CRC.


  • Integrated 1 SDIO2.0 Device controller, support SDIO1 bit / 4 bit / SPI three operating modes; working clock range 0~50MHz;
  • Integrated 2 UART interfaces, support RTS/CTS, baud rate range 1200bps~2Mbps;
  • Integrates a high-speed SPI device controller with an operating clock range of 0~50MHz;
  • Integrated with 1 SPI master/slave interface, the main device operating frequency supports 20Mpbs, and the slave device supports 6Mbps data transmission rate;
  • Integrated with an I 2 C controller supporting 100/400Kbps speed;
  • Integrated GPIO controller;
  • Integrated PWM controller with 5 PWM outputs or 2 PWM inputs. The highest output frequency is 20MHz, and the highest input frequency is 20MHz.
  • Integrated duplex I2S controller supporting 32KHz to 192KHz I2S interface codec;
  • Integrated 7816 interface, support ISO-7816-3 T=0/1 mode, support EVM2000 specification, and compatible with serial port function.